Register 87: Ethernet PHY Specific Control- MR17 (EPHYSCR), address 0x011
This register implements the PHY Specific Control register. This register allows access to general
functionality inside the PHY to enable operation in reduced power modes and control the interrupt
mechanism.
Ethernet PHY Specific Control- MR17 (EPHYSCR)
Base n/a
Address 0x011
Type RW, reset 0x0103
0123456789101112131415
reservedINTENTINTreservedCOLFDMreservedLBFIFOreservedSBPYASSPSMODEPSENDISCLK
RORWRWRORWRORORORWRWRORWRWRWRWRWType
0100000000010000Reset
DescriptionResetTypeNameBit/Field
Disable CLK
DescriptionValue
Normal mode of operation0
Disable internal clocks1
Clocks can be disabled only in IEEE power down mode.
0RWDISCLK15
Power Saving Modes Enable
DescriptionValue
Normal mode of operation0
Enable power saving modes1
0RWPSEN14
Power Saving Modes
DescriptionValue
Normal: Normal operation mode. PHY is fully functional0x0
IEEE Power Down
Low Power mode that shuts down all internal circuitry other than
SMI functionality. Power could be dropped further by setting
high DISCLK bit in this register and disabling internal clocks
circuitries.
0x1
Active Sleep
Low Power Active Wake-On-LAN (WOL) mode that shuts down
all internal circuitry other than SMI and energy detect
functionality. In this mode the PHY sends NLP every 1.4
seconds to wake up the link-partner. Automatic power-up is
done when link partner is detected.
0x2
Passive Sleep
Low Power WOL mode that shuts down all internal circuitry
besides SMI and energy detect functionality. Automatic power-up
is done when link partner is detected.
0x3
0RWPSMODE13:12
1619June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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