Register 25: GPIO Select Interrupt (GPIOSI), offset 0x538
This register is used to enable individual interrupts for each pin.
Note: This register is only available on Port P and Port Q.
GPIO Select Interrupt (GPIOSI)
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (AHB) base: 0x4006.0000
GPIO Port K (AHB) base: 0x4006.1000
GPIO Port L (AHB) base: 0x4006.2000
GPIO Port M (AHB) base: 0x4006.3000
GPIO Port N (AHB) base: 0x4006.4000
GPIO Port P (AHB) base: 0x4006.5000
GPIO Port Q (AHB) base: 0x4006.6000
Offset 0x538
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
SUMreserved
RWROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:1
Summary Interrupt
DescriptionValue
All port pin interrupts are OR'ed together to produce a summary
interrupt.
0
Note: The OR'ed summary interrupt occurs on bit 0 of the
GPIORIS register. For summary interrupt mode,
software should set the GPIOIM register to 0xFF and
mask the port pin interrupts 1 through 7 in the
Interrupt Clear Enable (DISn) register (see “NVIC
Register Descriptions” on page 153). When servicing
this interrupt, write a 1 to the corresponding bit in the
UNPENDn register to clear the pending interrupt in
the NVIC and clear the GPIORIS register pin interrupt
bits by setting the IC field of the GPIOICR register to
0xFF.
Each pin has its own interrupt vector.1
0RWSUM0
791June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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