Register 4: System Exception Interrupt Clear (SYSEXCIC), offset 0x00C
The SYSEXCIC register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
System Exception Interrupt Clear (SYSEXCIC)
Base 0x400F.9000
Offset 0x00C
Type W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
W1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CType
0000000000000000Reset
0123456789101112131415
FPIDCICFPDZCICFPIOCICFPUFCICFPOFCICFPIXCICreserved
W1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00W1Creserved31:6
Floating-Point Inexact Exception Interrupt Clear
Writing a 1 to this bit clears the FPIXCRIS bit in the SYSEXCRIS register
and the FPIXCMIS bit in the SYSEXCMIS register.
0W1CFPIXCIC5
Floating-Point Overflow Exception Interrupt Clear
Writing a 1 to this bit clears the FPOFCRIS bit in the SYSEXCRIS register
and the FPOFCMIS bit in the SYSEXCMIS register.
0W1CFPOFCIC4
Floating-Point Underflow Exception Interrupt Clear
Writing a 1 to this bit clears the FPUFCRIS bit in the SYSEXCRIS register
and the FPUFCMIS bit in the SYSEXCMIS register.
0W1CFPUFCIC3
Floating-Point Invalid Operation Interrupt Clear
Writing a 1 to this bit clears the FPIOCRIS bit in the SYSEXCRIS register
and the FPIOCMIS bit in the SYSEXCMIS register.
0W1CFPIOCIC2
Floating-Point Divide By 0 Exception Interrupt Clear
Writing a 1 to this bit clears the FPDZCRIS bit in the SYSEXCRIS register
and the FPDZCMIS bit in the SYSEXCMIS register.
0W1CFPDZCIC1
Floating-Point Input Denormal Exception Interrupt Clear
Writing a 1 to this bit clears the FPIDCRIS bit in the SYSEXCRIS register
and the FPIDCMIS bit in the SYSEXCMIS register.
0W1CFPIDCIC0
June 18, 2014530
Texas Instruments-Production Data
Processor Support and Exception Module