Register 83: Floating-Point Default Status Control (FPDSC), offset 0xF3C
The FPDSC register holds the default values for the Floating-Point Status Control (FPSC) register.
Floating-Point Default Status Control (FPDSC)
Base 0xE000.E000
Offset 0xF3C
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reservedRMODEFZDNAHPreserved
RORORORORORORWRWRWRWRWROROROROROType
000000-----00000Reset
0123456789101112131415
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:27
AHP Bit Default
This bit holds the default value for the AHP bit in the FPSC register.
-RWAHP26
DN Bit Default
This bit holds the default value for the DN bit in the FPSC register.
-RWDN25
FZ Bit Default
This bit holds the default value for the FZ bit in the FPSC register.
-RWFZ24
RMODE Bit Default
This bit holds the default value for the RMODE bit field in the FPSC
register.
DescriptionValue
Round to Nearest (RN) mode0x0
Round towards Plus Infinity (RP) mode0x1
Round towards Minus Infinity (RM) mode0x2
Round towards Zero (RZ) mode0x3
-RWRMODE23:22
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved21:0
June 18, 2014206
Texas Instruments-Production Data
Cortex-M4 Peripherals