Register 5: Ethernet MAC MII Address (EMACMIIADDR), offset 0x010
The Ethernet MAC MII address (EMACMIIADDR) register controls the management cycles to the
PHY through the management interface.
Ethernet MAC MII Address (EMACMIIADDR)
Base 0x400E.C000
Offset 0x010
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MIIBMIIWCRMIIPLA
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:16
Physical Layer Address
This field gives the PHY address of the MII module. Values 1- 31 (0x1
to 0x1F) are available for external PHY addresses.
Note: The integrated PHY's address is 0x00. To access the
integrated PHY registers, the PLA bits[15:11] must be zeros.
0x0RWPLA15:11
MII Register
These bits select the desired MII registers in the selected PHY device.
0x0RWMII10:6
Clock Reference Frequency Selection
The clock that is sent to the MAC Clock and Status (CSR) registers is
the gated System Clock (SYSCLK). The SYSCLK is divided down
through the CR field to produce an MDC clock that is approximately
between the frequency range 1.0 MHz - 2.5 MHz. The application must
program the appropriate CR field based on the System Clock input.
DescriptionValue
The frequency of the System Clock is 60 to 100 MHz providing
a MDIO clock of SYSCLK/42.
0x0
The frequency of the System Clock is 100 to 150 MHz
providing a MDIO clock of SYSCLK/62.
0x1
The frequency of the System Clock is 20-35 MHz providing
a MDIO clock of System Clock/16.
0x2
The frequency of the System Clock is 35 to 60 MHz providing
a MDIO clock of System Clock/26.
0x3
reserved0x4-0xF
0x0RWCR5:2
June 18, 20141484
Texas Instruments-Production Data
Ethernet Controller
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