Register 23: Ethernet MAC MMC Control (EMACMMCCTRL), offset 0x100
The MMC Control register establishes the operating mode of the management counters.
Note: The CNTRST bit has higher priority than the CNTPRST. Therefore, when the software tries
to set both bits in the same write cycle, all counters are cleared and the CNTPRST is not
set.
Ethernet MAC MMC Control (EMACMMCCTRL)
Base 0x400E.C000
Offset 0x100
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CNTRST
CNTSTPRO
RSTONRD
CNTFREEZ
CNTPRST
CNTPRSTLVL
reservedUCDBCreserved
RWRWRWRWRWRWRORORWROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:9
Update MMC Counters for Dropped Broadcast Frames
DescriptionValue
MMC Counters are not updated for dropped broadcast frames.0
MAC updates all related MMC counters for broadcast frames
dropped due to setting of DBF bit (Disable Broadcast Frames)
of the MAC Frame Filter(EMACFRAMEFLTR) register.
1
0RWUCDBC8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7:6
June 18, 20141512
Texas Instruments-Production Data
Ethernet Controller
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