Register 88: Ethernet PHY MII Interrupt Status 1 - MR18 (EPHYMISR1), address
0x012
This register contains events status and enables for the interrupt function. If an event has occurred
since the last read of this register, the corresponding status bit is set. If the corresponding enable
bit in the register is set, an interrupt is generated if the event occurs. The INTEN bit (Bit 1) in the
EPHYSCR register (0x011) must also be set to allow interrupts. The status indications in this register
are set even if the interrupt is not enabled.
Ethernet PHY MII Interrupt Status 1 - MR18 (EPHYMISR1)
Base n/a
Address 0x012
Type RW, reset 0x0000
0123456789101112131415
RXHFENFCHFENANCEN
DUPLEXMEN
SPEEDEN
LINKSTATEN
reservedRXHFFCHFANCDUPLEXMSPEED
LINKSTAT
reserved
RWRWRWRWRWRWROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:14
Change of Link Status Interrupt
Reading this bit clears the interrupt and thus, the status bit.
DescriptionValue
No change of link status.0
Change of link status interrupt is pending.1
0ROLINKSTAT13
Change of Speed Status Interrupt
Reading this bit clears the interrupt and thus, the status bit.
DescriptionValue
No change of speed status.0
Change of speed status interrupt is pending.1
0ROSPEED12
Change of Duplex Status Interrupt
Reading this bit clears the interrupt and thus, the status bit.
DescriptionValue
No change of duplex status.0
Duplex status change interrupt is pending.1
0RODUPLEXM11
Auto-Negotiation Complete Interrupt
Reading this bit clears the interrupt and thus, the status bit.
DescriptionValue
No Auto-negotiation complete event is pending.0
Auto-negotiation complete interrupt is pending.1
0ROANC10
June 18, 20141622
Texas Instruments-Production Data
Ethernet Controller
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