Texas Instruments TM4C1294NCPDT User Manual

Register 32: USB Power Domain Status (USBPDS), offset 0x280
This register provides the status of power to the USB SRAM memory array.
Note: If the USBMPC register's PWRCTL field is set to 0x3 and the power domain to the USB is
turned off by writing a 0 to the P0 bit of the PCUSB register, then the SRAM memory goes
into retention and the MEMSTAT field of the USBPDS register reads as 0x1 (retention).
USB Power Domain Status (USBPDS)
Base 0x400F.E000
Offset 0x280
Type RO, reset 0x0000.003F
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PWRSTATMEMSTATreservedreserved
ROROROROROROROROROROROROROROROROType
1111110000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x3ROreserved5:4
Memory Array Power Status
Displays status of USB SRAM memory
DescriptionValue
Array OFF0x0
SRAM Retention0x1
Reserved0x2
Array On0x3
0x3ROMEMSTAT3:2
Power Domain Status
DescriptionValue
OFF0x0
Reserved0x1-0x2
ON0x3
0x3ROPWRSTAT1:0
June 18, 2014312
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Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English