Register 39: CAN 1 Memory Power Control (CAN1MPC), offset 0x2A4
This register provides power control to the peripheral memory array.
Note: The CAN1 memory array does not support retention and can only be turned ON and OFF.
If the memory array is currently turned on (PWRCTL = 0x3) and the power control to CAN1
is subsequently removed by clearing the P1 bit of the PCCAN register, the event causes
the memory array to turn off and the MEMSTAT bit in the CAN1PDS register to be 0x0 (array
OFF).
CAN 1 Memory Power Control (CAN1MPC)
Base 0x400F.E000
Offset 0x2A4
Type RW, reset 0x0000.0003
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PWRCTLreserved
RWRWROROROROROROROROROROROROROROType
1100000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:2
Memory Array Power Control
Allows multiple levels of power control in peripheral's SRAM memory
space
DescriptionValue
Array OFF0x0
Reserved0x1-0x2
Array On0x3
0x3RWPWRCTL1:0
319June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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