Register 25: DMA Channel Map Select 3 (DMACHMAP3), offset 0x51C
Each 4-bit field of the DMACHMAP3 register configures the μDMA channel assignment as specified
in Table 9-1 on page 680.
Note: To support legacy software which uses the DMA Channel Assignment (DMACHASGN)
register, a value of 0x0 is equivalent to a DMACHASGN bit being clear, and a value of 0x1
is equivalent to a DMACHASGN bit being set.
DMA Channel Map Select 3 (DMACHMAP3)
Base 0x400F.F000
Offset 0x51C
Type RW, reset 0x0000.0000
16171819202122232425262728293031
CH28SELCH29SELCH30SELCH31SEL
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
0123456789101112131415
CH24SELCH25SELCH26SELCH27SEL
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
μDMA Channel 31 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH31SEL31:28
μDMA Channel 30 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH30SEL27:24
μDMA Channel 29 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH29SEL23:20
μDMA Channel 28 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH28SEL19:16
μDMA Channel 27 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH27SEL15:12
μDMA Channel 26 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH26SEL11:8
μDMA Channel 25 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH25SEL7:4
μDMA Channel 24 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH24SEL3:0
June 18, 2014732
Texas Instruments-Production Data
Micro Direct Memory Access (μDMA)