Texas Instruments TM4C1294NCPDT User Manual

Register 14: UART DMA Control (UARTDMACTL), offset 0x048
The UARTDMACTL register is the DMA control register.
UART DMA Control (UARTDMACTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x048
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RXDMAETXDMAEDMAERRreserved
RWRWRWROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00000.000ROreserved31:3
DMA on Error
DescriptionValue
µDMA receive requests are unaffected when a receive error
occurs.
0
µDMA receive requests are automatically disabled when a
receive error occurs.
1
0RWDMAERR2
Transmit DMA Enable
DescriptionValue
µDMA for the transmit FIFO is disabled.0
µDMA for the transmit FIFO is enabled.1
0RWTXDMAE1
Receive DMA Enable
DescriptionValue
µDMA for the receive FIFO is disabled.0
µDMA for the receive FIFO is enabled.1
0RWRXDMAE0
June 18, 20141208
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English