– ADC Module 1, ADCSPC = 0x0, sampling AIN1
Note: If two ADCs are configured to sample the same signal, a skew (phase lag) must be
added to one of the ADC modules to prevent coincident sampling. Phase lag can be
added by programming the PHASE field in the ADCSPC register.
■ Skewed sampling of the same signal. The skew is determined by both the TSHn field in the
ADCSSTSHn registers and the PHASE field in the ADCSPC register. For the fastest skewed
sample rate, all TSHn fields must be programmed to 0x0. If TSHn=0x0 for all sequencers and
the PHASE field of one ADC is 0x8, the configuration doubles the conversion bandwidth of a
single input when software combines the results as shown in Figure 15-5 on page 1061.
– ADC Module 0, ADCSPC = 0x0, sampling AIN0
– ADC Module 1, ADCSPC = 0x8, sampling AIN0
Note that it is not required that the TSHn fields be the same in a skewed sample. If an application
has varying analog input resistance, then TSHn and PHASE may vary according to operational
requirements.
Figure 15-5. Skewed Sampling
S1
S2
S2
S3
S3
S4
S4
S5
S5
S6
S6
S7
S7
S8
S8
ADC0
ADC1
S1
15.3.2.7 Module Clocking
The ADC digital block is clocked by the system clock and the ADC analog block is clocked from a
separate conversion clock (ADC Clock). The ADC clock frequency can be up to 32 MHz to generate
a conversion rate of 2 Msps. A 16 MHz ADC clock provides a 1 Msps sampling rate. There are three
sources of the ADC clock:
■ Divided PLL VCO. The PLL VCO frequency can be configured to generate up to a 32-MHz clock
for a conversion rate of 2 Msps. The CS field in the ADCCC register must be programmed to
0x0 to select the PLL VCO and the CLKDIV field is used to set the appropriate clock divisor for
the desired frequency.
1061June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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