Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004
This register shows the status of the raw interrupt signal of each sample sequencer. These bits may
be polled by software to look for interrupt conditions without sending the interrupts to the interrupt
controller.
ADC Raw Interrupt Status (ADCRIS)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x004
Type RO, reset 0x0000.0000
16171819202122232425262728293031
INRDCreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INR0INR1INR2INR3reservedDMAINR0DMAINR1DMAINR2DMAINR3reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000ROreserved31:17
Digital Comparator Raw Interrupt Status
DescriptionValue
All bits in the ADCDCISC register are clear.0
At least one bit in the ADCDCISC register is set, meaning that
a digital comparator interrupt has occurred.
1
0ROINRDC16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:12
SS3 DMA Raw Interrupt Status
DescriptionValue
The DMA interrupt has not occurred.0
The sample sequence 3 DMA interrupt is asserted.1
This bit is cleared by writing a 1 to the DMAINR3 bit in the ADCISC
register.
0RODMAINR311
SS2 DMA Raw Interrupt Status
DescriptionValue
The DMA interrupt has not occurred.0
The sample sequence 2 DMA interrupt is asserted.1
This bit is cleared by writing a 1 to the DMAINR2 bit in the ADCISC
register.
0RODMAINR210
1079June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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