DescriptionResetTypeNameBit/Field
SS1 DMA Raw Interrupt Status
DescriptionValue
The DMA interrupt has not occurred.0
The sample sequence 1 DMA interrupt is asserted.1
This bit is cleared by writing a 1 to the DMAINR1 bit in the ADCISC
register.
0RODMAINR19
SS0 DMA Raw Interrupt Status
DescriptionValue
The DMA interrupt has not occurred.0
The sample sequence 0 DMA interrupt is asserted.1
This bit is cleared by writing a 1 to the DMAINR0 bit in the ADCISC
register.
0RODMAINR08
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7:4
SS3 Raw Interrupt Status
DescriptionValue
An interrupt has not occurred.0
A sample has completed conversion and the respective
ADCSSCTL3 IEn bit is set, enabling a raw interrupt.
1
This bit is cleared by writing a 1 to the IN3 bit in the ADCISC register.
0ROINR33
SS2 Raw Interrupt Status
DescriptionValue
An interrupt has not occurred.0
A sample has completed conversion and the respective
ADCSSCTL2 IEn bit is set, enabling a raw interrupt.
1
This bit is cleared by writing a 1 to the IN2 bit in the ADCISC register.
0ROINR22
SS1 Raw Interrupt Status
DescriptionValue
An interrupt has not occurred.0
A sample has completed conversion and the respective
ADCSSCTL1 IEn bit is set, enabling a raw interrupt.
1
This bit is cleared by writing a 1 to the IN1 bit in the ADCISC register.
0ROINR11
June 18, 20141080
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
To Next Page
Loading...
