Texas Instruments TM4C1294NCPDT User Manual

Register 59: Ethernet MAC DMA Interrupt Mask Register (EMACDMAIM), offset
0xC1C
The Interrupt Enable register enables the interrupts reported by the MAC DMA Interrupt Status
Register (EMACDMARIS). Setting a bit to 0x1 enables a corresponding interrupt. After a hardware
or software reset, all interrupts are disabled.
Ethernet MAC DMA Interrupt Mask Register (EMACDMAIM)
Base 0x400E.C000
Offset 0xC1C
Type RW, reset 0x0000.0000
16171819202122232425262728293031
NIEreserved
RWROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TIETSETUETJEOVEUNERIERUERSERWEETEreservedFBEEREAIE
RWRWRWRWRWRWRWRWRWRWRWRORORWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:17
Normal Interrupt Summary Enable
DescriptionValue
Normal interrupt summary is masked.0
Normal interrupt summary is enabled.1
This bit enables/masks the ERI, RI, TU, and TI bits in MAC DMA
Interrupt Status Register (EMACDMARIS)
0x0RWNIE16
Abnormal Interrupt Summary Enable
DescriptionValue
Abnormal interrupt summary is disabled.0
Abnormal interrupt summary is enabled.1
This bit enables/masks the TPS, TJT, OVF, UNF, RU, RPS, RWT, ETI and
FBI bits in MAC DMA Interrupt Status Register (EMACDMARIS)
0x0RWAIE15
Early Receive Interrupt Enable
DescriptionValue
Early receive interrupt is disabled.0
Early receive interrupt is enabled. Normal Interrupt Summary
Enable (NIE, bit 16) must also be set to 0x1.
1
0x0RWERE14
June 18, 20141572
Texas Instruments-Production Data
Ethernet Controller

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English