DescriptionResetTypeNameBit/Field
Start or Stop Receive
When this bit is set, the Receive process is placed in the Running state.
The DMA attempts to acquire the descriptor from the Receive list and
processes the incoming frames. The descriptor acquisition is attempted
from the current position in the list, which is the address set by the
Receive Descriptor List Address Register (EMACRXDLADDR) or the
position retained when the Receive process was previously stopped. If
the DMA does not own the descriptor, reception is suspended and Bit
7 (Receive Buffer Unavailable, RU) of the MAC DMA Interrupt Status
Register (EMACDMARIS) is set. The Start Receive command is effective
only when the reception has stopped. If the command is issued before
setting EMACRXDLADDR, the DMA behavior is unpredictable.
When this bit is cleared, the receive DMA operation is stopped after the
transfer of the current frame. The next descriptor position in the Receive
list is saved and becomes the current position after the Receive process
is restarted. The Stop Receive command is effective only when the
Receive process is in either the Running (waiting for receive packet) or
in the Suspended state.
DescriptionValue
The receive DMA operation is stopped after the transfer of the
current frame
0
The Receive process is placed in the Running state.1
0x0RWSR1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved0
1571June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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