Figure 17-3. TI Synchronous Serial Frame Format (Continuous Transfer)
MSB
LSB
SSInClk
SSInFss
SSInTx/SSInRx
4 to 16 bits
17.3.7.2 Freescale SPI Frame Format
The Freescale SPI interface is a four-wire interface where the SSInFss signal behaves as a slave
select. If operating in Legacy Mode and using the Freescale SPI Frame Format, the inactive state
and phase of the SSInClk signal are programmable through the SPO and SPH bits in the SSICR0
control register. If operating in Advanced/Bi-/Quad-SSI mode, the SP0 and SPH bits must be
programmed to 0.
SPO Clock Polarity Bit
When the SPO clock polarity control bit is clear, it produces a steady state Low value on the SSInClk
pin. If the SPO bit is set, a steady state High value is placed on the SSInClk pin when data is not
being transferred.
SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state.
The state of this bit has the most impact on the first bit transmitted by either allowing or not allowing
a clock transition before the first data capture edge. When the SPH phase control bit is clear, data
is captured on the first clock edge transition. If the SPH bit is set, data is captured on the second
clock edge transition.
17.3.7.3 Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 17-4 on page 1236 and Figure 17-5 on page 1236.
Note: This is the only Freescale SPI frame format configuration that can be used when operating
in Advanced/Bi-/Quad-SSI mode.
1235June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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