7.3.9 Power Control Using VDD3ON Mode
The Hibernation module may also be configured to cut power to all internal modules during Hibernate
mode. While in this state, if VDD3ON is set in the HIBCTL register, all pins are held in the state they
were in prior to entering hibernation. For example, inputs remain inputs; outputs driven high remain
driven high, and so on. There are important procedural and functional items to note when in VDD3ON
mode:
■ JTAG Ports C[0] - C[3] do not retain their state in Hibernate VDD3ON mode.
■ If GPIO pins K[7:4] are not used as a wake source, they should not be left floating. An internal
pull-up resistor may be configured by the application before entering Hibernate mode by
programming the GPIO Pull-Up Select (GPIOPUR) register in the GPIO module.
■ In the VDD3ON mode, the regulator should maintain 3.3 V power to the microcontroller during
Hibernate. GPIO retention is disabled when the RETCLR bit is cleared in the HIBCTL register.
■ When entering hibernation in VDD3ON mode, the supply rails to the Ethernet resistors R1, R2,
R3, R4 found in Figure 20-13 on page 1464 must be switched off.
7.3.10 Initiating Hibernate
Hibernate mode is initiated when the HIBREQ bit of the HIBCTL register is set. If a wake-up condition
has not been configured using the PINWEN or RTCWEN bits in the HIBCTL register, the hibernation
request is ignored. In addition, if the battery voltage is below the threshold voltage defined by the
VBATSEL field in the HIBCTL register, the hibernation request is ignored.
7.3.11 Waking from Hibernate
The Hibernation module can be configured to wake from Hibernate mode if any of the following are
enabled:
■ External WAKE
■ External RST
■ GPIO K[7:4]
■ Tamper TMPR[3:0]
■ Tamper XOSC failure
The Hibernation module can also be configured to wake from hibernate when the following events
occur:
■ RTC match wake event
■ Low Battery wake event
The external WAKE pin is enabled by setting the PINWEN bit in the HIBCTL register. The external
WAKE pin can generate an interrupt by programming the EXTWEN bit in the Hibernation Interrupt
Mask (HIBIM) register.
Note: If an external WAKE signal is asserted, the application is responsible for clearing the signal
source once the EXTWEN bit has been registered in the Hibernation Raw Interrupt Status
(HIBRIS) register.
June 18, 2014546
Texas Instruments-Production Data
Hibernation Module
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