Figure 5-6. Module Clock Selection
Deep Sleep
Module Clock
System Clock
Clock Control Register
PIOSC or
ALTCLK
Baud Clock
0
0
1
1
Additional power management modes are available that lower the power consumption of the
peripheral memory, Flash, and SRAM memory. However, the lower power consumption modes
have slower deep-sleep and wake-up times.
Note: If one or more wait states are configured for Run Mode, then when the device enters
Deep-Sleep mode, it will achieve its lowest possible current. If there are no wait states
applied in Run mode, then lowest possible current is not achieved.
5.2.6.4 Dynamic Power Management
In addition to the Sleep and Deep-Sleep modes and the clock gating for the on-chip modules, there
are several additional power mode options that allow the LDO, Flash memory, and SRAM into
different levels of power savings while in Sleep or Deep-Sleep modes. In addition, software has the
ability to control the LDO settings to gain a power advantage when running at slower speeds. Note
that these features may not be available on all devices; the System Properties (SYSPROP) register
provides information on whether a mode is supported on a given MCU. The following registers
provide these capabilities:
■ Peripheral Power Control (PCx): Controls power to peripheral if that peripheral has the ability
to respond to a power request.
■ Peripheral Memory Power Control (xMPC): Provides power control to some the peripheral
memory arrays.
■ LDO Sleep Power Control (LDOSPCTL): Controls the LDO value in Sleep mode
■ LDO Deep-Sleep Power Control (LDODPCTL): Controls the LDO value in Deep-Sleep mode
■ LDO Sleep Power Calibration (LDOSPCAL): Provides factory recommendations for the LDO
value in Sleep mode
June 18, 2014242
Texas Instruments-Production Data
System Control
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