Register 80: Analog-to-Digital Converter Software Reset (SRADC), offset 0x538
The SRADC register provides software the capability to reset the available ADC modules.
A peripheral is reset by software using a simple two-step process:
1. Software sets a bit (or bits) in the SRADC register. While the SRADC bit is 1, the peripheral is
held in reset.
2. Software completes the reset process by clearing the SRADC bit.
There may be latency from the clearing of the SRADC bit to when the peripheral is ready for use.
Software should check the corresponding PRADC bit to verify that the ADC Module registers are
ready to be accessed.
Important: This register should be used to reset the ADC modules.
Analog-to-Digital Converter Software Reset (SRADC)
Base 0x400F.E000
Offset 0x538
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
R0R1reserved
RWRWROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:2
ADC Module 1 Software Reset
DescriptionValue
ADC module 1 is not reset.0
ADC module 1 is reset.1
0RWR11
ADC Module 0 Software Reset
DescriptionValue
ADC module 0 is not reset.0
ADC module 0 is reset.1
0RWR00
June 18, 2014372
Texas Instruments-Production Data
System Control
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