Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030
Each bit of the DMAALTSET register represents the corresponding µDMA channel. Setting a bit
configures the µDMA channel to use the alternate control data structure. Reading the register returns
the status of which control data structure is in use for the corresponding µDMA channel.
DMA Channel Primary Alternate Set (DMAALTSET)
Base 0x400F.F000
Offset 0x030
Type RW, reset 0x0000.0000
16171819202122232425262728293031
SET[n]
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
0123456789101112131415
SET[n]
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Channel [n] Alternate Set
DescriptionValue
µDMA channel [n] is using the primary control structure.0
µDMA channel [n] is using the alternate control structure.1
Bit 0 corresponds to channel 0. A bit can only be cleared by setting the
corresponding CLR[n] bit in the DMAALTCLR register.
Note: For Ping-Pong and Scatter-Gather cycle types, the µDMA
controller automatically sets these bits to select the alternate
channel control data structure.
0x0000.0000RWSET[n]31:0
723June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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