Register 41: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3),
offset 0x0A0
This register, along with the ADCSSEMUX3 register, defines the analog input configuration for the
sample in a sequence executed with Sample Sequencer 3. If the EMUX0 bit in the ADCSSEMUX3
register is set, the MUX0 field in this register selects from AIN[19:16]. When the EMUX0 bit is clear,
the MUX0 field selects from AIN[15:0]. This register is four bits wide and contains information for
one possible sample. See the ADCSSMUX0 register on page 1109 for detailed bit descriptions.
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0A0
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MUX0reserved
RWRWRWRWROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:4
1st Sample Input Select0RWMUX03:0
1141June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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