Texas Instruments TM4C1294NCPDT - Register 17: QSSI Peripheral Identification 0 (Ssiperiphid0), Offset 0 Xfe0

Register 17: QSSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
QSSI Peripheral Identification 0 (SSIPeriphID0)
QSSI0 base: 0x4000.8000
QSSI1 base: 0x4000.9000
QSSI2 base: 0x4000.A000
QSSI3 base: 0x4000.B000
Offset 0xFE0
Type RO, reset 0x0000.0022
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID0reserved
ROROROROROROROROROROROROROROROROType
0100010000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:8
QSSI Peripheral ID Register [7:0]
Can be used by software to identify the presence of this peripheral.
0x22ROPID07:0
1267June 18, 2014
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TM4C1294NCPDT Microcontroller