Register 12: Hibernation Data (HIBDATA), offset 0x030-0x06F
This address space is implemented as a 16x32-bit memory (64 bytes). It can be loaded by the
system processor in order to store state information and retains its state during a power cut operation
as long as a battery is present. HIBDATA registers 0x050 to 0x064 (upper eight words) may only
be accessed using the processor privileged mode (default).
Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the WRC bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 535. The HIBIO register and bits RSTWK, PADIOWK and
WC of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL
register has been set may produce unexpected results.
Note: If V
DD
is arbitrarily removed while a HIBDATA register write operation is in progress, the
write operation must be retried after V
DD
is reapplied.
Hibernation Data (HIBDATA)
Base 0x400F.C000
Offset 0x030-0x06F
Type RW, reset -
16171819202122232425262728293031
RTD
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
----------------Reset
0123456789101112131415
RTD
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
----------------Reset
DescriptionResetTypeNameBit/Field
Hibernation Module NV Data-RWRTD31:0
June 18, 2014574
Texas Instruments-Production Data
Hibernation Module
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