Register 51: Ethernet MAC PPS0 Width (EMACPPS0WIDTH), offset 0x764
The MAC PPS0 Width (EMACPPS0WIDTH) register contains the number of units of sub-second
increment value between the rising and corresponding falling edges of the EN0PPS output signal.
Note: The PTP reference clock referred to below is MOSC clock in course update mode and in
fine correction mode, is the clock tick at which the system time gets updated.
Ethernet MAC PPS0 Width (EMACPPS0WIDTH)
Base 0x400E.C000
Offset 0x764
Type RW, reset 0x0000.0000
16171819202122232425262728293031
PPS0WIDTH
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
0123456789101112131415
PPS0WIDTH
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
EN0PPS Output Signal Width
These bits store the width between the rising edges and corresponding
falling edge of the of the EN0PPS signal output in terms of units of
sub-second increment value.
It must be programmed one value less than the required interval. For
example, if the PTP reference clock is 25 MHz (period of 40 ns), and
the desired interval between rising edges of EN0PPS signal output is 80
ns (that is, two units of sub-second increment value), then you should
program value 1 (2 -1) in this register.
Note: The value programmed in this register must be less than the
value programmed in the Ethernet MAC PPS0 Interval
(EMACPPS0INTVL) register, offset 0x760.
0x0RWPPS0WIDTH31:0
June 18, 20141552
Texas Instruments-Production Data
Ethernet Controller
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