Texas Instruments TM4C1294NCPDT User Manual

Register 3: ADC Interrupt Mask (ADCIM), offset 0x008
This register controls whether the sample sequencer and digital comparator raw interrupt signals
are sent to the interrupt controller. Each raw interrupt signal can be masked independently.
Note: For a 1 to 2 Msps rate, as the system clock frequency approaches the ADC clock frequency,
it is recommended that the application use the µDMA to store conversion data from the
FIFO to memory before processing rather than an interrupt-driven single data read. Using
the µDMA to store multiple samples before interrupting the processor amortizes interrupt
overhead across multiple transfers and prevents loss of sample data.
Note: Only a single DCONSSn bit should be set at any given time. Setting more than one of these
bits results in the INRDC bit from the ADCRIS register being masked, and no interrupt is
generated on any of the sample sequencer interrupt lines. It is recommended that when
interrupts are used, they are enabled on alternating samples or at the end of the sample
sequence.
ADC Interrupt Mask (ADCIM)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x008
Type RW, reset 0x0000.0000
16171819202122232425262728293031
DCONSS0DCONSS1DCONSS2DCONSS3reserved
RWRWRWRWROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MASK0MASK1MASK2MASK3reserved
DMAMASK0DMAMASK1DMAMASK2DMAMASK3
reserved
RWRWRWRWRORORORORWRWRWRWROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000ROreserved31:20
Digital Comparator Interrupt on SS3
DescriptionValue
The status of the digital comparators does not affect the SS3
interrupt status.
0
The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS3 interrupt line.
1
0RWDCONSS319
Digital Comparator Interrupt on SS2
DescriptionValue
The status of the digital comparators does not affect the SS2
interrupt status.
0
The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS2 interrupt line.
1
0RWDCONSS218
June 18, 20141082
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Analog-to-Digital Converter (ADC)

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English