a new or next byte is written to the RX FIFO, thus the counter will continue to count down to zero
unless there is new activity. The time-out period is 32 periods based on the period of SSInClk.
When the counter reaches zero, a time-out interrupt bit, RTRIS, is set in the SSIRIS register. The
time-out interrupt can be cleared by writing a 1 to the RTIC bit of the SSI Interrupt Clear (SSIIC)
register or by emptying the RX FIFO. If the interrupt is cleared and there is residual data left in the
RX FIFO or new data entries have been written, the timer count down initiates and the interrupt will
be reasserted after 32 periods have been counted.
The End-of-Transmission (EOT) interrupt indicates that the data has been transmitted completely
and is only valid for Master mode devices/operations. This interrupt can be used to indicate when
it is safe to turn off the QSSI module clock or enter sleep mode. In addition, because transmitted
data and received data complete at exactly the same time, the interrupt can also indicate that read
data is ready immediately, without waiting for the receive FIFO time-out period to complete.
Note: In Freescale SPI mode only, a condition can be created where an EOT interrupt is generated
for every byte transferred even if the FIFO is full. If the the µDMA has been configured to
transfer data from this QSSI to a Master QSSI on the device using external loopback, an
EOT interrupt is generated by the QSSI slave for every byte even if the FIFO is full.
17.3.7 Frame Formats
Each data frame is between 4 and 16 bits long in Legacy mode and 8-bits in Advanced/Bi-/Quad-
SSI mode and is transmitted starting with the MSB. There are two basic frame types that can be
selected by programming the FRF bit in the SSICR0 register:
■ Texas Instruments synchronous serial
■ Freescale SPI
Note: Advanced, Bi- and Quad-SSI modules only supports Freescale mode when SPH=0; SPO=0
and DDS=0x8 in the SSI Control 0 (SSICR0) register.
For both formats, the serial clock (SSInClk) is held inactive while the QSSI is idle, and SSInClk
transitions at the programmed frequency only during active transmission or reception of data. The
idle state of SSInClk is utilized to provide a receive timeout indication that occurs when the receive
FIFO still contains data after a timeout period.
For Freescale SPI frame format, the serial frame (SSInFss) pin is active Low, and is asserted
(pulled down) during the entire transmission of the frame.
For Texas Instruments synchronous serial frame format, the SSInFss pin is pulsed for one serial
clock period starting at its rising edge, prior to the transmission of each frame. For this frame format,
both the QSSI and the off-chip slave device drive their output data on the rising edge of SSInClk
and latch data from the other device on the falling edge.
The following table gives a synopsis of the features supported in each frame format when operating
in Legacy Mode:
Table 17-4. Legacy Mode TI, Freescale SPI Frame Format Features
Freescale SPI ModeTI ModeFeature
AvailableNot AvailableFrame Hold
AvailableNot AvailableHigh Speed (Master RX Only)
Available and can be used in combination with
Frame Hold and High Speed Mode
Not AvailableSPO/SPH Configuration
1233June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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