Register 11: QSSI Peripheral Properties (SSIPP), offset 0xFC0
The SSIPP register provides information regarding the properties of the QSSI module.
QSSI Peripheral Properties (SSIPP)
QSSI0 base: 0x4000.8000
QSSI1 base: 0x4000.9000
QSSI2 base: 0x4000.A000
QSSI3 base: 0x4000.B000
Offset 0xFC0
Type RO, reset 0x0000.000D
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
HSCLKMODE
FSSHLDFRM
reserved
ROROROROROROROROROROROROROROROROType
1011000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0000ROreserved31:4
SSInFss Hold Frame Capability
DescriptionValue
SSInFss Hold Frame capability disabled.0
SSinFss Hold Frame capability enabled.1
0x1ROFSSHLDFRM3
Mode of Operation
Indicates what QSSI functionality is supported.
DescriptionValue
Legacy SSI mode0x0
Legacy mode, Advanced SSI mode and Bi-SSI mode enabled.0x1
Legacy mode, Advanced mode, Bi-SSI and Quad-SSI mode
enabled.
0x2
reserved0x3
0x2ROMODE2:1
High Speed Capability
DescriptionValue
High Speed clock capability disabled.0
High speed clock capability enabled.1
0x1ROHSCLK0
1261June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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