Register 35: Ethernet MAC Memory Power Control (EMACMPC), offset 0x28C
This register provides power control to the peripheral memory array.
Note: The EMAC memory array does not support retention and can only be turned ON and OFF.
Memory array OFF is supported only when the power domain is off. If the memory array is
turned on (PWRCTL = 0x3) and the power control to the EMAC is removed by clearing the
P0 bit of the PCEMAC register, the memory array is turned off and the MEMSTAT bit in the
EMACPDS register is 0x0.
Ethernet MAC Memory Power Control (EMACMPC)
Base 0x400F.E000
Offset 0x28C
Type RW, reset 0x0000.0003
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PWRCTLreserved
RWRWROROROROROROROROROROROROROROType
1100000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:2
Memory Array Power Control
DescriptionValue
Array OFF0x0
Note: Array OFF Mode is only supported when the P0 bit
of the PCEMAC register at offset 0x99C is set to
0.
Reserved0x1-0x2
Array On0x3
0x3RWPWRCTL1:0
315June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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