Register 26: LDO Sleep Power Calibration (LDOSPCAL), offset 0x1B8
This register provides factory determined values that are recommended for the VLDO field in the
LDOSPCTL register while in Sleep mode. The reset value of this register cannot be determined
until the product has been characterized.
LDO Sleep Power Calibration (LDOSPCAL)
Base 0x400F.E000
Offset 0x1B8
Type RO, reset 0x0000.1818
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
NOPLLWITHPLL
ROROROROROROROROROROROROROROROROType
0001100000011000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:16
Sleep with PLL
The value in this field is the suggested value for the VLDO field in the
LDOSPCTL register when using the PLL. This value provides the lowest
recommended LDO output voltage for use with the PLL at the maximum
specified value.
0x18ROWITHPLL15:8
Sleep without PLL
The value in this field is the suggested value for the VLDO field in the
LDOSPCTL register when not using the PLL. This value provides the
lowest recommended LDO output voltage for use without the PLL.
0x18RONOPLL7:0
June 18, 2014302
Texas Instruments-Production Data
System Control
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