Register 167: EPI Peripheral Ready (PREPI), offset 0xA10
The PREPI register indicates whether the EPI module is ready to be accessed by software following
a change in status of power, Run mode clocking, or reset. A power change is initiated if the
corresponding PCEPI bit is changed from 0 to 1. A Run mode clocking change is initiated if the
corresponding RCGCEPI bit is changed. A reset change is initiated if the corresponding SREPI bit
is changed from 0 to 1.
The PREPI bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
EPI Peripheral Ready (PREPI)
Base 0x400F.E000
Offset 0xA10
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
R0reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:1
EPI Module Peripheral Ready
DescriptionValue
The EPI module is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
0
The EPI module is ready for access.1
0ROR00
503June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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