Register 13: Ethernet MAC Interrupt Mask (EMACIM), offset 0x03C
The Ethernet MAC Interrupt Mask (EMACIM) Register bits enables the application to mask the
interrupt signal caused by the corresponding event in the Ethernet MAC Raw Interrupt Status
(EMACRIS) Register.
Ethernet MAC Interrupt Mask (EMACIM)
Base 0x400E.C000
Offset 0x03C
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedPMTreservedTSIreserved
RORORORWRORORORORORWROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0ROreserved31:10
Timestamp Interrupt Mask
DescriptionValue
The TSI interrupt status bit in the MAC Raw Interrupt Status
(EMACRIS) register is not masked and can cause an interrupt.
0
The assertion of the TIS interrupt status bit in the MAC Raw
Interrupt Status (EMACRIS) register is masked and does not
cause an interrupt.
1
0x0RWTSI9
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved8:4
PMT Interrupt Mask
DescriptionValue
The PMT interrupt status bit in the MAC Raw Interrupt Status
(EMACRIS) register is not masked and can cause an interrupt.
0
The assertion of the PMT interrupt status bit in the MAC Raw
Interrupt Status (EMACRIS) register is masked and does not
cause an interrupt.
1
0x0RWPMT3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2:0
1499June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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