DescriptionResetTypeNameBit/Field
Deep Sleep Clock Divisor
This field specifies the system clock divisor value during deep sleep
mode. The clock source selected by DSOSCSRC is divided by DSSYSDIV
+ 1:
f
SYSCLK
=f
OSCCLK
/(DSSYSDIV + 1)
Note: Values 0x0 and 0x1 should not be used. If Deep-Sleep clock
divide by 1 or divide by 2 is desired, the OSYSDIV bit field of
the RSCLKCFG register must be configured for the desired
Deep-Sleep divider before entering Deep-Sleep. In this case,
the Q post-divider bit field in the PLLFREQ1 register may
need to be adjusted to keep the system clock frequency within
the maximum clock frequency before entering Deep-Sleep.
0x0RWDSSYSDIV9:0
283June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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