Register 29: EEPROM Interrupt (EEINT), offset 0x040
The EEINT register is used to control whether an interrupt should be generated when a write to
EEPROM completes as indicated by the EEDONE register value changing from 0x1 to any other
value. If the INT bit in this register is set, the ERIS bit in the Flash Controller Raw Interrupt Status
(FCRIS) register is set whenever the EEDONE register value changes from 0x1 as the Flash memory
and the EEPROM share an interrupt vector.
EEPROM Interrupt (EEINT)
Base 0x400A.F000
Offset 0x040
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INTreserved
RWROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:1
Interrupt Enable
DescriptionValue
No interrupt is generated.0
An interrupt is generated when the EEDONE register transitions
from 1 to 0 or an error occurs. The EEDONE register provides
status after a write to an offset location as well as a write to the
password and protection bits.
1
0RWINT0
663June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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