Register 71: Ethernet PHY Masked Interrupt Status and Clear (EPHYMISC),
offset 0xFD8
The Ethernet Masked Interrupt Status and Clear (EPHYMISC) register displays the masked
interrupt status of the integrated Ethernet PHY and can written to clear the EPHYRIS register..
This register is used for clearing the EPHYRIS register bits.
Ethernet PHY Masked Interrupt Status and Clear (EPHYMISC)
Base 0x400E.C000
Offset 0xFD8
Type RW1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INTreserved
RW1CROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:1
Ethernet PHY Status and Clear register
Reading this register provides a result which is the logical AND of the
EPHYRIS and EPHYIM registers. A write of 1 to a bit of this register
clears the corresponding bit in the EPHYRIS register.
Note: The Ethernet MAC interrupt is an OR'd summary of both the
masked EMACRIS register output and this register. When an
Ethernet MAC interrupt is asserted, software mush check
both the EMACRIS and EMACIM registers along with this
register.
0RW1CINT0
20.8 Ethernet PHY Register Descriptions
This section lists and describes the PHY registers, in numerical order by address. Also see “Ethernet
MAC Register Descriptions” on page 1470.
1589June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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