Register 22: DMA Channel Map Select 0 (DMACHMAP0), offset 0x510
Each 4-bit field of the DMACHMAP0 register configures the μDMA channel assignment as specified
in Table 9-1 on page 680.
Note: To support legacy software which uses the DMA Channel Assignment (DMACHASGN)
register, a value of 0x0 is equivalent to a DMACHASGN bit being clear, and a value of 0x1
is equivalent to a DMACHASGN bit being set.
DMA Channel Map Select 0 (DMACHMAP0)
Base 0x400F.F000
Offset 0x510
Type RW, reset 0x0000.0000
16171819202122232425262728293031
CH4SELCH5SELCH6SELCH7SEL
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
0123456789101112131415
CH0SELCH1SELCH2SELCH3SEL
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
μDMA Channel 7 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH7SEL31:28
μDMA Channel 6 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH6SEL27:24
μDMA Channel 5 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH5SEL23:20
μDMA Channel 4 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH4SEL19:16
μDMA Channel 3 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH3SEL15:12
μDMA Channel 2 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH2SEL11:8
μDMA Channel 1 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH1SEL7:4
μDMA Channel 0 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH0SEL3:0
729June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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