Register 10: EPI Address Map (EPIADDRMAP), offset 0x01C
This register enables address mapping. The EPI controller can directly address memory and
peripherals. In addition, the EPI controller supports address mapping to allow indirect accesses in
the External RAM and External Peripheral areas.
If the external device is a peripheral, including a FIFO or a directly addressable device, the EPSZ
and EPADR bit fields should be configured for the address space. If the external device is SDRAM,
SRAM, or NOR Flash memory, the ERADR and ERSZ bit fields should be configured for the address
space.
If one of the dual chip select modes is selected (CSCFGEXT is 0x0 and CSCFG is 0x2 or 0x3 in the
EPIHBnCFG2 register), both chip selects can share the peripheral or the memory space, or one
chip select can use the peripheral space and the other can use the memory space. In the
EPIADDRMAP register, if the EPADR field is not 0x0, the ECADR field is 0x0, and the ERADR field is
0x0, then the address specified by EPADR is used for both chip selects, with CS0n being asserted
when the MSB of the address range is 0 and CS1n being asserted when the MSB of the address
range is 1. If the ERADR field is not 0x0, the ECADR field is 0x0, and the EPADR field is 0x0, then the
address specified by ERADR is used for both chip selects, with the MSB performing the same
delineation. If both the EPADR and the ERADR are not 0x0 and the ECADR field is 0x0, then CS0n is
asserted for either address range defined by EPADR and CS1n is asserted for either address range
defined by ERADR. The two chip selects can also be shared between the code space and memory
or peripheral space. If the ECADR field is 0x1, ERADR field is 0x0, and the EPADR field is not 0x0,
then CS0n is asserted for the address range defined by ECADR and CS1n is asserted for either
address range defined by EPADR. If the ECADR field is 0x1, EPADR field is 0x0, and the ERADR field
is not 0x0, then CS0n is asserted for the address range defined by ECADR and CS1n is asserted
for either address range defined by ERADR.
If one of the Quad-Chip-Select modes is selected (CSCFGEXT is 0x1 and CSCFG is 0x2 or 0x3 in
the EPIHBnCFG2 register), both the peripheral and the memory space must be enabled. In the
EPIADDRMAP register, the EPADR field is 0x3, the ERADR field is 0x3, and the ECADR field is 0x0.
In this case, CS0n maps to 0x6000.0000; CS1n maps to 0x8000.0000; CS2n maps to 0xA000.0000;
and CS3n maps to 0xC000.0000. The MODE field of the EPIHBnCFGn registers configures the
interface for the individual chip selects, which support ADMUX or ADNOMUX. If the CSBAUD bit is
clear, all chip selects use the mode configured in the MODE bit field of the EPIHBnCFG register.
Table 11-5 on page 828 gives a detailed explanation of chip select address range mappings based
on which combinations of peripheral and memory space are enabled.
EPI Address Map (EPIADDRMAP)
Base 0x400D.0000
Offset 0x01C
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ERADRERSZEPADREPSZECADRECSZreserved
RWRWRWRWRWRWRWRWRWRWRWRWROROROROType
0000000000000000Reset
June 18, 2014892
Texas Instruments-Production Data
External Peripheral Interface (EPI)
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