Register 165: General-Purpose Input/Output Peripheral Ready (PRGPIO),
offset 0xA08
The PRGPIO register indicates whether the GPIO modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A power change is initiated if
the corresponding PCGPIO bit is changed from 0 to 1. A Run mode clocking change is initiated if
the corresponding RCGCGPIO bit is changed. A reset change is initiated if the corresponding
SRGPIO bit is changed from 0 to 1.
The PRGPIO bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
General-Purpose Input/Output Peripheral Ready (PRGPIO)
Base 0x400F.E000
Offset 0xA08
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
R0R1R2R3R4R5R6R7R8R9R10R11R12R13R14reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:15
GPIO Port Q Peripheral Ready
DescriptionValue
GPIO Port Q is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
0
GPIO Port Q is ready for access.1
0ROR1414
GPIO Port P Peripheral Ready
DescriptionValue
GPIO Port P is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
0
GPIO Port P is ready for access.1
0ROR1313
GPIO Port N Peripheral Ready
DescriptionValue
GPIO Port N is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
0
GPIO Port N is ready for access.1
0ROR1212
499June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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