Register 36: EPI Host-Bus 8 Configuration 4 (EPIHB8CFG4), offset 0x30C
Important: The MODE field in the EPICFG register determines which configuration is enabled.
For EPIHB8CFG4 to be valid, the MODE field must be 0x2.
EPI Host-Bus 8 Configuration 4 (EPIHB8CFG4)
Base 0x400D.0000
Offset 0x30C
Type RW, reset 0x0008.0000
16171819202122232425262728293031
reservedALEHIGHRDHIGHWRHIGHreserved
RORORORWRWRWROROROROROROROROROROType
0001000000000000Reset
0123456789101112131415
MODEreservedRDWSWRWSreserved
RWRWRORORWRWRWRWROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:22
CS3n WRITE Strobe Polarity
This field is used if the CSBAUD bit is enabled in EPIHB8CFG2.
DescriptionValue
The WRITE strobe for CS3n accesses is WRn (active Low).0
The WRITE strobe for CS3n accesses is WR (active High).1
0RWWRHIGH21
CS2n READ Strobe Polarity
This field is used if the CSBAUD bit is enabled in EPIHB8CFG2.
DescriptionValue
The READ strobe for CS3n accesses is RDn (active Low).0
The READ strobe for CS3n accesses is RD (active High).1
0RWRDHIGH20
CS3n ALE Strobe Polarity
This field is used if the CSBAUD bit is enabled in EPIHB8CFG2
DescriptionValue
The address latch strobe for CS3n accesses is ADVn (active
Low).
0
The address latch strobe for CS3n accesses is ALE (active
High).
1
1RWALEHIGH19
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved18:8
June 18, 2014922
Texas Instruments-Production Data
External Peripheral Interface (EPI)
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