Figure 20-9. System Time Update Using Fine Correction Method
EMACTIMADD
Accumulator Register
Constant Value
EMACTIMNANO
EMACTIMSEC
+
+
EMACTIMSTCTRL.
ADDREGUP
Increment the
Sub-Seconds Register
Increment the
Seconds Register
Note: The MOSC clock that feeds the PTP reference clock to the System Time Module must be
25 MHz because it is also clocks the integrated PHY module.
Initially, the Ethernet's slave clock (from the MOSC) is adjusted with a compensation value (as
described in the previous paragraph) which is written to the Timestamp Addend Register (TSAR)
field in the EMACTIMADD register. This value is calculated as: FreqCompensationValue
0
= TSAR
= 2
32
/ FreqDivisionRatio.
The System Time Module requires a 20-MHz PTP reference clock frequency to achieve 50-ns
accuracy in the fine correction method. An addend must be written to the Ethernet MAC Time
Stamp Addend (EMACTIMADD) register, offset 0x718 to achieve timing synchronization. If the
MOSC clock source is 25 MHz, the frequency division ratio (FreqDivisionRatio) of the two is calculated
as 25 MHz / 20 MHz = 1.25. Hence, the default addend value to be set in the register is 2
32
/ 1.25
or 0xCCCC.CCD0. If the reference clock drifts lower, to 24 MHz for example, the ratio is 24 / 20, or
1.2 and the value to set in the addend register is 2
32
/ 1.20, or 0xDFF1.65D2. The software must
calculate the drift in frequency based on the Sync messages and update the EMACTIMADD register,
at offset 0x718, accordingly.
If the master to slave delay is initially assumed to be the same for consecutive Sync messages,
then the following steps can be used to calculate a new TSAR value. The following algorithm
calculates the precise mater to slave delay value to allow for re-synchronization with the master
using the new value:
1443June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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