Texas Instruments TM4C1294NCPDT - Register 23: Deep-Sleep Power Configuration (DSLPPWRCFG), Offset 0 X18 C

Register 23: Deep-Sleep Power Configuration (DSLPPWRCFG), offset 0x18C
This register provides configuration information for the power control of the SRAM and Flashmemory
while in Deep-Sleep mode.
Deep-Sleep Power Configuration (DSLPPWRCFG)
Base 0x400F.E000
Offset 0x18C
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
SRAMPMreservedFLASHPMreservedTSPDLDOSMreserved
RWRWRORORWRWRORORWRWROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:10
LDO Sleep Mode
DescriptionValue
LDO is disabled in sleep-mode.0
LDO is placed in a low power mode when deep sleep mode is
entered.
1
0RWLDOSM9
Temperature Sense Power Down
This bit controls low power mode for the internal temperature sensor in
the ADC.
DescriptionValue
Temperature sensor in the ADC is disabled in sleep-mode.0
The internal temperature sensor in the ADC is placed in a low
power mode when deep sleep mode is entered.
1
0RWTSPD8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved7:6
297June 18, 2014
Texas Instruments-Production Data
Tiva
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TM4C1294NCPDT Microcontroller