Texas Instruments TM4C1294NCPDT User Manual

Register 3: System Exception Masked Interrupt Status (SYSEXCMIS), offset
0x008
The SYSEXCMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
System Exception Masked Interrupt Status (SYSEXCMIS)
Base 0x400F.9000
Offset 0x008
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
FPIDCMISFPDZCMISFPIOCMISFPUFCMISFPOFCMISFPIXCMIS
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:6
Floating-Point Inexact Exception Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to an inexact
exception.
1
This bit is cleared by writing a 1 to the FPIXCIC bit in the SYSEXCIC
register.
0ROFPIXCMIS5
Floating-Point Overflow Exception Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to an overflow
exception.
1
This bit is cleared by writing a 1 to the FPOFCIC bit in the SYSEXCIC
register.
0ROFPOFCMIS4
Floating-Point Underflow Exception Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to an underflow
exception.
1
This bit is cleared by writing a 1 to the FPUFCIC bit in the SYSEXCIC
register.
0ROFPUFCMIS3
June 18, 2014528
Texas Instruments-Production Data
Processor Support and Exception Module

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English