Register 12: Ethernet MAC Raw Interrupt Status (EMACRIS), offset 0x038
The Ethernet MAC Raw Interrupt Status (EMACRIS) register identifies the events in the MAC
that can generate interrupt.
Ethernet MAC Raw Interrupt Status (EMACRIS)
Base 0x400E.C000
Offset 0x038
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedPMTMMCMMCRXMMCTXreservedTSreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0ROreserved31:10
Timestamp Interrupt Status
This bit is cleared by reading the TSSOVF bit in the MAC timestamp
Status Register (EMACTIMSTAT) register.
In this mode, this bit is cleared after the completion of the read of this
bit. In all other modes, this bit is reserved.
DescriptionValue
No timestamp interrupt is present.0
When the advanced timestamp feature is enabled, this bit
indicates one of two conditions is true:
1
■ The system time value equals or exceeds the value
specified in the EMAC Target Time Seconds Register
(EMACTARGSEC) and MAC Target Time Nanoseconds
(EMACTARGNANO) registers.
■ There is an overflow in the EMAC Target Time Seconds
(EMACTARGSEC) register.
When default timestamping is enabled, this bit indicates that
the system time value is equal to or exceeds the value specified
in the EMAC Target Time registers. In this mode, this bit is
cleared after the completion of the read of this bit.
0x0ROTS9
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved8:7
1497June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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