DescriptionResetTypeNameBit/Field
MMC Transmit Interrupt Status
This bit is cleared when all of the bits in the MAC MMC Transmit
Interrupt (EMACMMCTXRIS) register are clear.
DescriptionValue
No interrupts exist in the MAC MMC Transmit Interrupt
(EMACMMCTXRIS) register.
0
Indicates an interrupt has been generated in the MAC MMC
Transmit Interrupt (EMACMMCTXRIS) register.
1
0ROMMCTX6
MMC Receive Interrupt Status
This bit is cleared when all of the bits in the Ethernet MAC MMC
Receive Interrupt (EMACMMCRXRIS) register are clear.
DescriptionValue
No interrupts exist in the MAC MMC Receive Interrupt
(EMACMMCTXRIS) register.
0
Indicates an interrupt has been generated in the MAC MMC
Receive Interrupt (EMACMMCRXRIS) register.
1
0ROMMCRX5
MMC Interrupt Status
DescriptionValue
Indicates the MMC-related Interrupt bits [6:5] in this register are
clear.
0
Indicates that one or more of the MMC-related interrupt bits
[6:5] in this register are set.
1
0x0ROMMC4
PMT Interrupt Status
DescriptionValue
This bit is cleared when both Bits[6:5] are cleared because of
a read operation to the MAC PMT Control and Status Register
(EMACPMTCTRLSTAT) register.
0
Indicates a Magic packet or Wake-on-LAN frame is received in
the power-down mode (see Bits 5 and 6 in the
MACPMTCTRLSTAT register).
1
0x0ROPMT3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved2:0
June 18, 20141498
Texas Instruments-Production Data
Ethernet Controller
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