DescriptionResetTypeNameBit/Field
Fatal Bus Error Enable
DescriptionValue
Fatal Bus Error Enable Interrupt is disabled.0
Fatal Bus Error Interrupt is enabled. Abnormal Interrupt
Summary Enable (AIE, bit 15) must also be set to 0x1.
1
0x0RWFBE13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved12:11
Early Transmit Interrupt Enable
DescriptionValue
Early Transmit Interrupt is disabled.0
Early Transmit Interrupt is enabled. Abnormal Interrupt Summary
Enable (AIE, bit 15) must also be set to 0x1.
1
0x0RWETE10
Receive Watchdog Timeout Enable
DescriptionValue
The Receive Watchdog Timeout Interrupt is disabled.0
The Receive Watchdog Timeout Interrupt is enabled. Abnormal
Interrupt Summary Enable (AIE, bit 15) must also be set to 0x1.
1
0x0RWRWE9
Receive Stopped Enable
DescriptionValue
Receive Stopped Interrupt is disabled.0
Receive Stopped Interrupt is enabled. Abnormal Interrupt
Summary Enable (AIE, bit 15) must also be set to 0x1.
1
0x0RWRSE8
Receive Buffer Unavailable Enable
DescriptionValue
The Receive Buffer Unavailable Interrupt is disabled.0
The Receive Buffer Unavailable Interrupt is enabled. Abnormal
Interrupt Summary Enable (AIE, bit 15) must also be set to 0x1.
1
0x0RWRUE7
Receive Interrupt Enable
DescriptionValue
The Receive Interrupt is disabled.0
The Receive Interrupt is enabled. Normal Interrupt Summary
Enable (NIE, bit 15) must also be set to 0x1.
1
0x0RWRIE6
1573June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller