DescriptionResetTypeNameBit/Field
Invalid Data Masked Interrupt Status and Clear
DescriptionValue
When read, a 0 indicates that an interrupt has not occurred.
A write of 0 has no effect on the state of this bit.
0
When read, a 1 indicates that an unmasked interrupt was
signaled.
Writing a 1 to this bit clears INVDMISC and also the INVDRIS
bit in the FCRIS register (see page 630).
1
0RW1CINVDMISC10
VOLT Masked Interrupt Status and Clear
DescriptionValue
When read, a 0 indicates that an interrupt has not occurred.
A write of 0 has no effect on the state of this bit.
0
When read, a 1 indicates that an unmasked interrupt was
signaled.
Writing a 1 to this bit clears VOLTMISC and also the VOLTRIS
bit in the FCRIS register (see page 630).
1
0RW1CVOLTMISC9
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved8:3
EEPROM Masked Interrupt Status and Clear
DescriptionValue
When read, a 0 indicates that an interrupt has not occurred.
A write of 0 has no effect on the state of this bit.
0
When read, a 1 indicates that an unmasked interrupt was
signaled.
Writing a 1 to this bit clears EMISC and also the ERIS bit in the
FCRIS register (see page 630).
1
0RW1CEMISC2
Programming Masked Interrupt Status and Clear
DescriptionValue
When read, a 0 indicates that a programming cycle complete
interrupt has not occurred.
A write of 0 has no effect on the state of this bit.
0
When read, a 1 indicates that an unmasked interrupt was
signaled because a programming cycle completed.
Writing a 1 to this bit clears PMISC and also the PRIS bit in the
FCRIS register (see page 630).
1
0RW1CPMISC1
June 18, 2014636
Texas Instruments-Production Data
Internal Memory