DescriptionResetTypeNameBit/Field
Write Masked Interrupt Status
DescriptionValue
The number of available entries in the WFIFO is above the range
specified by the trigger level or the interrupt is masked.
0
The number of available entries in the WFIFO is within the range
specified by the trigger level (the WRFIFO field in the
EPIFIFOLVL register) and the WRIM bit in the EPIIM register is
set, triggering an interrupt to the interrupt controller.
1
0ROWRMIS2
Read Masked Interrupt Status
DescriptionValue
The number of valid entries in the NBRFIFO is below the range
specified by the trigger level or the interrupt is masked.
0
The number of valid entries in the NBRFIFO is within the range
specified by the trigger level (the RDFIFO field in the
EPIFIFOLVL register) and the RDIM bit in the EPIIM register is
set, triggering an interrupt to the interrupt controller.
1
0RORDMIS1
Error Masked Interrupt Status
DescriptionValue
An error has not occurred or the interrupt is masked.0
A WFIFO Full, a Read Stalled, or a Timeout error has occurred
and the ERIM bit in the EPIIM register is set, triggering an
interrupt to the interrupt controller.
1
0ROERRMIS0
June 18, 2014912
Texas Instruments-Production Data
External Peripheral Interface (EPI)
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