DescriptionResetTypeNameBit/Field
QSSI Direction of Operation
DescriptionValue
TX (Transmit Mode) write direction0
RX (Receive Mode) read direction1
0RWDIR8
QSSI Mode
DescriptionValue
Legacy SSI mode0x0
Bi-SSI mode0x1
Quad-SSI Mode0x2
Advanced SSI Mode with 8-bit packet size0x3
0x0RWMODE7:6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved5:3
QSSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
the QSSI is disabled (SSE=0).
DescriptionValue
The QSSI is configured as a master.0
The QSSI is configured as a slave.1
0RWMS2
QSSI Synchronous Serial Port Enable
DescriptionValue
QSSI operation is disabled.0
QSSI operation is enabled.1
Note: The HSCLKEN bit in the SSICR1 register should be
set only after applying reset to the QSSI module and
enabling the QSSI by setting the SSE bit, and before
any SSI data transfer. All other bits in the SSICR1
register and all bits in SSICR0 register can only be
programmed when the SSE is clear.
0RWSSE1
QSSI Loopback Mode
DescriptionValue
Normal serial port operation enabled.0
Output of the transmit serial shift register is connected internally
to the input of the receive serial shift register.
1
0RWLBM0
June 18, 20141248
Texas Instruments-Production Data
Quad Synchronous Serial Interface (QSSI)
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