DescriptionResetTypeNameBit/Field
GPIO Masked Interrupt Status
DescriptionValue
An interrupt condition on the corresponding pin is masked or
has not occurred.
0
An interrupt condition on the corresponding pin has triggered
an interrupt to the interrupt controller.
1
For edge-detect interrupts, this bit is cleared by writing a 1 to the
corresponding bit in the GPIOICR register.
For a GPIO level-detect interrupt, the bit is cleared when the level is
deasserted.
0x00ROMIS7:0
June 18, 2014768
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
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