Table 5-18. Module Power Control ........................................................................................ 456
Table 5-19. Module Power Control ........................................................................................ 461
Table 5-20. Module Power Control ........................................................................................ 463
Table 5-21. Module Power Control ........................................................................................ 465
Table 5-22. Module Power Control ........................................................................................ 467
Table 5-23. Module Power Control ........................................................................................ 470
Table 5-24. Module Power Control ........................................................................................ 472
Table 5-25. Module Power Control ........................................................................................ 476
Table 5-26. Module Power Control ........................................................................................ 478
Table 5-27. Module Power Control ........................................................................................ 480
Table 5-28. Module Power Control ........................................................................................ 482
Table 5-29. Module Power Control ........................................................................................ 484
Table 5-30. Module Power Control ........................................................................................ 486
Table 5-31. Module Power Control ........................................................................................ 488
Table 5-32. Module Power Control ........................................................................................ 490
Table 5-33. Module Power Control ........................................................................................ 492
Table 5-34. Module Power Control ........................................................................................ 494
Table 6-1. System Exception Register Map ......................................................................... 523
Table 7-1. Hibernate Signals (128TQFP) ............................................................................. 534
Table 7-2. HIB Clock Source Configurations ........................................................................ 535
Table 7-3. Hibernation Module Register Map ....................................................................... 552
Table 8-1. MEMTIM0 Register Configuration versus Frequency ............................................ 605
Table 8-2. Flash Memory Protection Policy Combinations .................................................... 610
Table 8-3. User-Programmable Flash Memory Resident Registers ....................................... 614
Table 8-4. MEMTIM0 Register Configuration versus Frequency ............................................ 617
Table 8-5. Master Memory Access Availability ..................................................................... 621
Table 8-6. Flash Register Map ............................................................................................ 622
Table 9-1. μDMA Channel Assignments .............................................................................. 680
Table 9-2. Request Type Support ....................................................................................... 682
Table 9-3. Control Structure Memory Map ........................................................................... 684
Table 9-4. Channel Control Structure .................................................................................. 684
Table 9-5. μDMA Read Example: 8-Bit Peripheral ................................................................ 693
Table 9-6. μDMA Interrupt Assignments .............................................................................. 694
Table 9-7. Channel Control Structure Offsets for Channel 30 ................................................ 695
Table 9-8. Channel Control Word Configuration for Memory Transfer Example ...................... 696
Table 9-9. Channel Control Structure Offsets for Channel 7 .................................................. 697
Table 9-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 697
Table 9-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 699
Table 9-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive
Example ............................................................................................................ 699
Table 9-13. μDMA Register Map .......................................................................................... 701
Table 10-1. GPIO Pins With Special Considerations .............................................................. 743
Table 10-2. GPIO Pins and Alternate Functions (128TQFP) ................................................... 743
Table 10-3. GPIO Drive Strength Options .............................................................................. 753
Table 10-4. GPIO Pad Configuration Examples ..................................................................... 754
Table 10-5. GPIO Interrupt Configuration Example ................................................................ 755
Table 10-6. GPIO Pins With Special Considerations .............................................................. 756
Table 10-7. GPIO Register Map ........................................................................................... 757
June 18, 201418
Texas Instruments-Production Data
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